This application in the U.S. national phase of International Application No. PCT/GB99/04275, filed Dec. 16, 1999, the entire content of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to methods of driving a array of optical elements. It has particular but not exclusive relevance to the driving of a spatial light modulator.
2. Discussion of Prior Art
The spatial light modulator to be described in relation to a preferred embodiment in this specification is a in the form of a smectic liquid crystal layer disposed between an active semiconductor backplane and a common front electrode. It was developed in response to a requirement for a fast and, if possible, inexpensive, spatial light modulator comprising a relatively large number of pixels with potential application not only as a display device, but also for other forms of optical processing such as correlation and holographic switching. Other aspects of this device are dealt with in our copending International Patent Applications of even filing and priority dates (PCT/GB99/04285, U.S. Ser. No. 09/868,219, priority GB9827952.4; PCT/GB99/04286 and PCT/GB99/04276, U.S. Ser. No. 09/868,230 and U.S. Ser. No. 09/868,220, both priority GB9827965.6; PCT/GB99/04282, U.S. Ser. Nos. 09/446,325 and 10/084,652, priority GB9827900.3; PCT/GB99/04279, U.S. Ser. No. 10/085,140, priority GB9827901.1; PCT/GB99/04274, U.S. Ser. Nos. 09/868,218 and 10/094,958, priority GB9827964.9; and PCT/GB99/04260 and PCT/GB99/04277, U.S. Ser. No. 09/868,242, both priority GB 9827944.1).
During the course of development of this spatial light modulator, a series of problems were encountered and dealt with, and the solutions to these problems (whether in the form of construction, function or method) are not necessarily restricted in application to the embodiment, but will find other uses. Thus not all of the aspects of the present invention are necessarily limited to liquid crystal devices, nor to spatial light modulators. Nevertheless, it is useful to commence with a discussion of the problems encountered in developing the embodiment to be described later.
The liquid crystal phase has been recognised since the last century, and there were a few early attempts to utilise liquid crystal materials in light modulators, none of which gave rise to any significant successful commercial use. However, towards the end of the 1960""s and in the 1970""s, there was a renewed interest in the use of liquid crystal materials in light modulating, with increasing success as more materials, and purer materials became available, and as technology in general progressed.
Generally speaking, this latter period commenced with the use of nematic and cholesteric liquid crystal materials. Cholesteric liquid crystal materials found use as sensors, principally for measuring temperature or indicating a temperature change, but also for responding to, for example, the presence of impurities. In such cases, the pitch of the cholesteric helix is sensitive to the parameter to be sensed and correspondingly alters the wavelength at which there is selective reflection of one hand of circularly polarised light by the helix.
Attempts were also made to use cholesteric materials in electro-optic modulators, but during this period the main thrust of research in this area involved nematic materials. Initial devices used such effects as the nematic dynamic scattering effect, and increasingly sophisticated devices employing such properties as surface induced alignment, the effect on polarised light, and the co-orientation of elongate dye molecules or other elongate molecules/particles, came into being.
Some such devices used cells in which the nematic phase adopted a twisted structure, either by suitably arranging surface alignments or by incorporating optically active materials in the liquid crystal phase. There is a sense in which such materials resemble cholesteric materials, which are often regarded as a special form of the nematic phase.
Initially, liquid crystal light modulators were in the form of a single cell comprising a layer of liquid crystal material sandwiched between opposed electrode bearing plates, at least one of the plates being transparent. Such cells were slow to operate and tended to have a short life due to degradation of the liquid crystal material. Quite early on it was recognised that the application of an average dc voltage to the liquid crystal cell was not beneficial, and at least in some cases produced degradation by electrolysis of the liquid crystal material itself, and schemes were evolved to render the average dc voltage to zero (dc balance).
It is now appreciated that other effects are also at work when a dc voltage is applied. When driving liquid crystal electro-optic devices for any length of time, a phenomenon known as image sticking may occur. Although the precise cause of this effect is unknown, there are theories that ions are trapped or a space charge is induced within the material in response to an overall dc field, and this results in a residual field even when the external dc field is removed. Whether to avoid electrolytic breakdown, or to avoid image sticking, it is evidently desirable that the time averaged voltage (that is, the average over the time that the voltage is actually being applied from an external source to the liquid crystal) applied to a liquid crystal material is zero.
The thickness of the liquid crystal layer in nematic cells is commonly around 20 to 100 microns, and there is a correspondingly small unit capacitance associated with a nematic liquid crystal cell. Furthermore, the switching time from a wholly xe2x80x9cOFFxe2x80x9d state to a wholly xe2x80x9cONxe2x80x9d state tends to be rather long, commonly around a millisecond. Relaxation back to the xe2x80x9cOFFxe2x80x9d state can be somewhat longer, unless positively driven, but the xe2x80x9cOFFxe2x80x9d state is the only stable one.
At the same time, electro-optic nematic devices comprising a plurality of pixels were being devised. Initially, these had the form of a common electrode on one side of a cell and a plurality of individually addressable passive electrodes on the other side of the cell (e.g. as in a seven-segment display), or, for higher numbers of pixels, intersecting passive electrode arrays on either side of the cell, for example row and column electrodes which were scanned. While the latter arrangements provided considerable versatility, there were problems associated with cross-talk between pixels.
The situation was exacerbated when analogue (grey scale) displays were required by analogue modulation of the applied voltage, since the optical response is non-linearly related to applied voltage. Addressing schemes became relatively complicated, particularly if dc balance was also required. Such considerations, in association with the relative slowness of switching of nematic cells, have made is difficult to provide real-time video images having a reasonable resolution.
Subsequently, active back-plane devices were produced. These comprise a layer of liquid crystal material disposed between a back plane and a spaced opposed substrate. The backplane comprises a plurality of active elements, such as transistors, for energising corresponding pixels. Energisation normally involves cooperation with one or more counterelectrodes disposed on the opposed substrate, although it would be possible to provide counterelectrodes in the backplane itself for fields generally parallel to the plane of the liquid crystal layer.
Two common forms of backplane are thin film transistor on silica/glass backplanes, and semiconductor backplanes. The active elements can be arranged to exercise some form of memory function, in which case addressing of the active element can be accelerated compared to the time needed to address and switch the pixel, easing the problem of displaying at video frame rates.
Active backplanes are commonly provided in an arrangement very similar to a dynamic random access memory (DRAM) or a static random access memory (SRAM). At each one of a distributed array of addressable locations, a SRAM type active backplane comprises a memory cell including at least two coupled transistors arranged to have two stable states, so that the cell (and therefore the associated liquid crystal pixel) remains in the last switched state until a later addressing step alters its state. Each location electrically drives its associated liquid crystal pixel, and is bistable per se, i.e. without the pixel capacitance. Power to drive the pixel to maintain the existing switched state is obtained from busbars which also supply the array of SRAM locations. Addressing is again normally performed from peripheral logic and column and row addressing lines.
In a DRAM type active backplane, a single active element (transistor) is provided at each location, and forms, together with the capacitance of the associated liquid crystal pixel, a charge storage cell. Thus in this case, and unlike a SRAM backplane, the liquid crystal pixels are an integral part of the DRAM of the backplane. There is no bistability associated with the location unless the liquid crystal pixel itself is bistable, and this is not the case so far as nematic pixels are concerned. Instead, reliance is placed on the active element providing a high impedance when it is not being addressed to prevent leakage of charge from the capacitance, and on periodic refreshing of the DRAM location.
In contrast to the type of RAM associated with computing, the pixel circuits, and more significantly the pixel transistors, are often at least partially exposed to light. This can lead to problems, especially with DRAM type backplanes where the pixels are part of the DRAM circuit, including photo-induced conductivity and charge leakage. This aspect is dealt with in greater detail in our copending application PCT/GB99/04279, U.S. Ser. No. 10/085,140.
Thin film transistor (TFT) backplanes comprise an array of thin film transistors distributed on a substrate (commonly transparent) over what can be a considerable area, with peripheral logic circuits for addressing the transistors, thereby facilitating the provision of large area pixellated devices which can be directly viewed. Nevertheless, there are problems associated with the yields of the backplanes during manufacture, and the length of the addressing conductors has a slowing effect on the scanning. When provided on a transparent substrate, such as of glass, TFT arrays can actually be located on the front or rear surface of a liquid crystal display device.
In view of their overall size, the area of the TFT array occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors is relatively insignificant. There is therefore no significant disadvantage in employing the SRAM configuration as opposed to the DRAM configuration. This sort of backplane thus overcomes many of the problems associated with slow switching times of liquid crystal pixels.
Generally, the active elements in TFT backplanes are diffusion transistors and the like as opposed to FETS, so that the associated impedances are relatively low and associated charge leakage relatively high in the xe2x80x9cOFFxe2x80x9d state.
Semiconductor active backplanes are limited in size to the size of semiconductor substrate available, and are not suited for direct viewing with no intervening optics. Nevertheless their very smallness aids speed of addressing of the active elements. This type of backplane commonly comprises FETs, for example MOSFETs or CMOS circuitry, with associated relatively high impedances in the xe2x80x9cOFFxe2x80x9d state.
However, the smallness also means that the area of the overall light modulation (array) area occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors can be relatively significant, particularly in the SRAM type which requires many more elements than the DRAM type. Being opaque to visible light, a semiconductor backplane would provide the rear substrate of a light modulator or display device.
At a later period still, substantial development occurred in the use of smectic liquid crystals. These have potential advantages over nematic phases insofar as their switching speed is markedly greater, and with appropriate surface stabilisation the ferroelectric smectic C phases should provide devices having two stable alignment states, i.e. a memory function.
The thickness of the layer of liquid crystal material in such devices is commonly much smaller than in the corresponding nematic devices, normally being of the order of a few microns at most. In addition to altering the potential switching speed, this increases the unit capacitance of a pixel, easing the function of a DRAM active backplane in retaining a switched state at a pixel until the next address occurs.
However, as the liquid crystal thickness approaches the thicknesses associated with the underlying structure of the backplane, and any possible deformation of the liquid crystal cell structure by flexing or other movement of the substrates, problems arise, for example as to the uniformity of response across the pixel area, and the capability for short circuiting across the cell thickness. These factors are dealt with in more detail in our copending applications PCT/GB99/04285, U.S. Ser. No. 09/868,219; and PCT/GB99/04282, U.S. Ser. Nos. 09/446,325 and 10/084,652.
The possibility of long relaxation times, or even of bistability, of the liquid crystal cell or pixel, facilitates the introduction of a relatively new digital technique when a grey scale image is required, in which pixels are turned xe2x80x9cONxe2x80x9d for a fraction of the viewing period according to the grey level. Essentially, the image is computationally decomposed to a series of bit planes in which each pixel is either xe2x80x9cONxe2x80x9d or xe2x80x9cOFFxe2x80x9d, the bit planes being sequentially displayed. In a preferred form, the (normally binary) weighted bit plane technique, the durations of the bit planes are weighted thereby reducing the number of bit planes required to synthesise an image, and reducing addressing requirements somewhat.
Pixel Structurexe2x80x94Switching and Address Times When using a SRAM type backplane to switch a capacitive element the time necessary to address the location on the backplane can be as small as is necessary to switch that location, regardless of whether the capacitive element has responded. The location is always coupled to the power supply, and can continue to supply power (current/voltage) to the capacitive element after the addressing pulse has ceased.
By contrast, power is supplied to a capacitive element from a DRAM location only while addressing is taking place, after which the active element (transistor) is turned off. If the addressing pulse is insufficiently long for transfer of the requisite amount of charge, the capacitive element is incompletely switched. This is likely to occur, for example, when the capacitive element includes ferroelectric material, as in some smectic liquid crystal cells, and the addressing time is short, for example in a large scale array.
One solution is to provide an additional xe2x80x9cslugxe2x80x9d capacitance which is rapidly charged during the addressing pulse and so can provide a reservoir of charge while the capacitive element switches over a longer time period. This aspect is dealt with in more detail in our copending application PCT/GB99/04279, U.S. Ser. No. 10/085,140, which relates to the provision of a semiconductor active backplane including an array of addressable active elements on a semiconductor substrate for energising respective first electrodes, wherein at least part of the region beneath a said electrode is adapted to act as a capacitor. In particular said part may be formed as a depletion region whereby in use it acts as a reverse biassed diode, or individual capacitor plates may be formed beneath the electrode, one coupled to the substrate and the other coupled to the electrode.
Smectic Liquid Crystal Electro-Optic Cells In the smectic liquid crystal phase, the molecules exhibit positional order (xe2x80x9clayersxe2x80x9d) in addition to the orientational order exhibited by the cholesteric and nematic phases. There are a number of different smectic sub-phases which differ in the orientational order within the overall structure of the smectic layers, the most common being the smectic A phase (SmA) and the smectic C phase (SmC).
The common alignment for smectic materials is planar (molecules generally parallel to the major cell surfaces) with the smectic layers normal to the plane of the cell, as this permits the field to be applied across the cell thickness. It is possible to obtain homeotropic alignment with the smectic layers in the cell plane, and such a device could provide a fast refractive index modulator. However, in order to apply appropriate electric fields for switching, very small electrode gaps are required and therefore such devices tend to have very small active areas, and as a consequence this type of device is relatively uncommon.
In the smectic A phase the director is normal to the plane of the layers. Application of an electric field perpendicular to the director causes the latter to tilt about an axis parallel to the applied field by an amount approximately linearly dependent of field strength, making it possible to achieve analogue grey scale modulation. Polarisation of the light is affected, so that intensity or phase modulation may be achieved, and since the rotation of the director is in the plane of the cell, normally incident light is always perpendicular to the optic axis of the material. Coupled with the thinness of the cell, this leads to improved viewing angles for such devices. This effect, called the electroclinic effect, is extremely fast, switching times down to around 100 nanoseconds having been observed.
In the smectic C phase, the director forms a constant (xe2x80x9ctiltxe2x80x9d) angle with the plane of the smectic layers. The tilt angle depends on the material and the temperature, and defines a cone with its tip on the smectic layer and its axis normal to the layer, all possible positions of the director lying on the cone surface. In the bulk of a chiral smectic C phase (SmC*) the director precesses from layer to layer as in a helix.
In the chiral smectic C phase, liquid crystal materials are ferro-electric, having a permanent dipole, sometimes termed spontaneous polarisation (Ps). In the bulk material, P, rotates in the plane of the layer as the director precesses, so no net effect is observable. Bulk ferro-electricity can be observed if the precession is suppressed, either by surface stabilisation of the director positions such that only the two orientations of director which lie in the plane of the device are possible, and/or by back-doping with a chiral material of the opposite hand.
Smectic C* materials can be broadly divided into two classes known as high and low tilt materials respectively. Class I materials have the phase sequence isotropic-nematic-smectic A*-smectic C*, and tend be low tilt materials, having tilt angles generally grouped up to around 22.5xc2x0 (cone angle of 45xc2x0); class II materials have the phase sequence isotropic-nematic-smectic C*, and tend to be high tilt materials with greater tilt angles. Materials with a cone angle greater than 75xc2x0 are rare, although for holographic applications, which require phase modulation, a cone angle of 90xc2x0 would be ideal.
With low tilt materials, the smectic layers are inclined relative to the cell surface rather than at right angles, such that the director cone has a tilted axis and its surface is tangential to the cell surface. For high tilt materials the cone axis is normal to the cell surface.
When the structure is surface stabilised, then in theory, at least for Class I materials there is no preference between the two states of a low tilt material and a bistable structure should result. Surface stabilisation can be achieved simply by making the layer in the cell thin. The two states will have different effects on polarised light, and so can provide intensity or phase modulation. In practice, it is very difficult or impossible to obtain true bistability, especially on silicon backplanes and there will a slight preference for one state over the other. Nevertheless, this should give rise to relatively long relaxation times.
For high tilt materials, the two states are not equal, and one state is preferred over the other, so that there is monostability in the absence of any other factor. The two states are such that phase modulation of light may be obtained, and, indirectly, intensity modulation, e.g. in holographic applications. Both high and low tilt materials may be used in the spatial light modulator of the invention.
Stability/Relaxation The presence of the spontaneous polarisation, and its realignment as the liquid crystal molecules realign under the influence of an electric field, leads to a significant additional current or charge flow during realignment, e.g. between electrodes either side of a smectic layer. A pixel of area A will consume a charge of 2APs during switching. This factor is particularly important when pixel switching is controlled by a DRAM type of active backplane, when pixel capacitance and Ps become important design parameters. It should also be noted that charge consumption reduces the field across the electrodes in such devices if the addressing pulse is insufficiently long to accommodate pixel switching, as in the present preferred embodiment.
As has already been noted, the use of the backplanes described herein is not limited to liquid crystal devices. However, these backplanes are particularly suited for use in the manufacture of liquid crystal devices. Again, although it is possible to employ nematic or cholesteric materials in such devices, it is preferred to employ smectic materials because of their faster switching action.
Other reasons for preferring smectic materials are the fast switching times; and, in the case of using a DRAM type active backplane (this does not apply when the backplane is the SRAM type since power/current can be continuously applied to each pixel), the ability to extend the relaxation time, or even to obtain a bistable effect, once the pixel has been placed in the desired state. One advantage of having a fast switching time in the case where relaxation occurs lies in the increase of the fraction of the pixel repeat address period usable for viewing time. Another advantage, particularly where optical processing is concerned is the increase in data throughput.
Electrostatic Stabilisation The charge consumption which occurs when a pixel is switched in one direction gives rise to a corresponding generation of charge when the pixel switches in the other direction. Therefore, if a switched pixel is completely electrically isolated, charge cannot flow and the pixel cannot relax. In operation of a DRAM type array, this may be effected by turning off all the transistors of the array, and in the preferred embodiment this is made possible by applying a global reset signal NRAR to the row scanners. Also, in some embodiments of addressing scheme, all the transistors are left in the off state once all the rows in the frame have been scanned, until the start of the next frame scan. (Other embodiments of addressing scheme, including those with ac stabilisation, do require transistors to be left on).
In practice, charge leakage cannot be completely eliminated, and so relaxation will occur, but over an extended period. A common cause of charge leakage is photoconductivity associated with the slug capacitance mentioned earlier and/or photoconductive or other leakage currents in the associated switching transistor of the DRAM array.
Electrical isolation is thus a useful but imperfect tool for prolonging relaxation times. It will be appreciated that whether a long relaxation time is achieved through an appropriate choice of material and cell design, or by electrical isolation, the important factor is that sufficient time can be allowed between successive addressings of any pixel for it to be maintained essentially in its desired state.
AC Stabilisation During relaxation, the director rotates out of the plane of the device to the alternative position. If an electric field is applied to a material, the field itself induces a polarisation of the material, and the polarisation reacts to the field, resulting in a torque that is proportional to the square of the field and so independent of field polarity. With a material having negative dielectric anisotropy this torque acts to maintain the molecule in the plane of the pixel, thereby xe2x80x9clockingxe2x80x9d the liquid crystal director orientation in either of its switched states. Thus the continuous application of an alternating electrical field between successive addressings (which at least in some cases is of low amplitude relative to the switching voltage) prevents relaxation of the director to the alternative orientation. Any tendency for the director to rotate from either of the two preferred orientations is effectively immediately counteracted by the ac field which returns the director to the orientation that it should have. The effect should obtain for as long as the ac field is present, so that the device behaves as if it were bistable.
In a DRAM array device this effect can be obtained by globally turning on all of the DRAM switching transistors, applying the same dc signal (e.g. zero or V volts) to all of the column electrodes, and by applying an ac voltage to the common front electrode with dc level corresponding to that applied to the column electrodes.
This endless prolongation of the switched pixel states is particularly important in certain types of optical processing where the same optical state may need to be maintained for days, months or even years.
It is therefore clear that during operation of the array it would be desirable to be able simultaneously to enable a plurality of the rows, and more preferably all the rows, so that all of the enabled pixels down each column may be brought simultaneously to the same state. This has already been mentioned in connection with the provision of blanking and ac stabilisation for prolonging the switched state of a pixel, and it is also desirable insofar as it permits the length of time that a dc pulse of potential is applied to be clearly and precisely defined, which is desirable when considering dc balancing. Following such enabling, and where as stabilisation is not used, it is also desirable to disable the enabled transistors, preferably a global disable over the entire array, to prevent relaxation due to short circuiting of a liquid crystal cell, for example.
In the embodiment to be described hereafter, where the parallel data fed to the columns is identical, and all of the rows are enabled, the whole array can be brought to zero or one, thereby blanking the array. If the parallel data along the columns is varied, a vertically striped image is produced.
If the potential difference between the front electrode and the columns during blanking is zero, the pixels will be short circuited, thereby permitting relaxation to take place. Alternatively, the potential difference may be a positive or negative dc, thus driving all of the pixels relatively rapidly on or off. If the dc potential difference is zero but a small ac voltage is present, preferably on the common front electrode for ease of application, in certain circumstances the pixels can be maintained in their existing states, as described in more detail elsewhere in this specification (ac stabilisation).
Our copending application PCT/GB99/04274, U.S. Ser. Nos. 09/868,218 and 10/094,958 relates to the provision of an array of electrically addressable elements, said array comprising a plurality of mutually exclusive sets of said elements, means arranged to address said sets one at a time, and means for addressing more than one (and preferably all) of said plurality of sets (the xe2x80x9cselected setsxe2x80x9d) simultaneously. While the most common form of array is arranged as addressable rows (the sets) and columns, other arrangements are possible, for example based on polar co-ordinates (distance and angle). However, modern computing methods and standards converters have tended to make other formats redundant in the majority of cases.
Although, as will be seen, the facility of being able to address all pixels of the array simultaneous is highly desirable in practising the methods of the present invention, it is not essential, and there are cases where the simultaneous addressing step could be replaced by a further writing operation.
The present invention is intended to facilitate the achievement of dc balance while driving an array of binary elements.
In a first aspect, the present invention provides a method of writing an array of optical elements in a succession of cycles to alter their states according to respective ones of a series of input data sets, each cycle comprising a first step wherein selected elements only of an optically blank of uniform array are written as determined by a respective data set, and a second step wherein the selected elements are selectively erased to restore a blank array prior to another cycle.
In a second aspect, the invention provides an electro-optic arrangement comprising an array of electro-optic elements and control means responsive to a series of input data sets, the control means being arranged to respond to each data set so that starting with an optically blank or uniform array of elements in a first step selected elements are written as determined by the data set, and in a second step the selected elements are selectively erased to revert to a blank array prior to writing elements as determined by a successive data set.
The array of optical/electro-optic elements may comprise a corresponding array of addressable active elements (e.g. pixel electrodes for example formed on an active backplane, preferably a semiconductor backplane), and an electrode spaced from said corresponding array, each optical/electro-optic element being defined between said electrode and a corresponding active element. The spaced electrode may be common to all elements of the array.
In one preferred form of the method, during the first step the active elements and the spaced electrode are operated to apply a first potential difference across the selected optical/electro-optic elements, and during the second step the active elements and the spaced electrode are operated to apply a second potential difference across the selected elements, the first and second potential differences having opposite signs, and, preferably, equal amplitudes.
More preferably, the potential applied to the spaced electrode may be switched between first and second values, with the output of the whole array of addressable active elements also being similarly switched between said first and second values of potential substantially synchronously with the switching of the front electrode. The potential applied to said first electrode may have the second value only during said second step.
The optical/electro-optic elements may comprise liquid crystal material located between the array and the spaced electrode, and they may be bistable or monostable.
It is desirable that between the first and second steps all the elements of the array are simultaneously addressed to impose zero potential difference thereacross. This serves effectively to provide a defined period for each individual element during which dc has been applied across it, and so enables dc balance to be more precisely determined.
In the preferred embodiment, the array comprises a plurality of mutually exclusive sets of the optical/electro-optic elements, means arranged to address the sets one at a time, and means for addressing more than one (and preferably all) of said plurality of sets (the xe2x80x9cselected setsxe2x80x9d) simultaneously. In such a case, a preferred method of producing a binary image includes the step of simultaneously addressing all the elements of the array once they have been written. During this step the elements are subjected to a common signal such that they receive (a) an ac signal, for ac stabilisation; or, for electrostatic stabilisation or for other purposes (for example providing a clearly defined time during which a dc signal is applied for dc balancing purposes) either (b) zero volts; or (c) a finite dc voltage. Where dc or zero volts is applied, this may be subsequently terminated by application of an ac stabilising signal, or by turning the elements off, i.e. open circuit, for electrostatic stabilisation.
UK Patent Application Serial No GB2247974A is directed to refreshing an existing image in a manner designed to avoid dc imbalance, effectively involving image reversal. It is not directed to writing of a new image or images, nor is there any teaching concerning the writing of a succession of (different) images so as to maintain dc balance. In a first embodiment all elements of the array are addressed by a positive or negative voltage during each array scan. In cases where there is a fixed front electrode voltage, it is understood that all the column electrodes are addressed with positive or negative voltages so as to write a full (inverted or negative) array of pixels in the normal way during a single scan, followed by rewriting of the non-inverted image. In cases where there is an alternating front electrode voltage, after driving all pixels to the same optical state (blanking), the state of a selected set pixels is reversed to give a fully written array. The array is subsequently blanked to the opposite optical state and the state of the complementary set of pixels is reversed to give the same optical written array. This type of blanking is unnecessary in the present invention.
UK Patent Application Serial No. GB2173336A is also concerned with dc balancing of liquid crystals which switch only above a threshold voltage. A row, or set of rows is blanked, followed by the application of column data in the form of dc balanced bipolar data pulses together with a dc strobe pulse on the row. The latter pulse coacts with one of the bipolar data pulses but not with the other, to change the state of a pixel. The overall polarity of the set-up, including the polarity of the strobe and blanking pulses, is periodically inverted (regularly or randomly) to maintain overall dc balance. The methods of present invention do not necessitate blanking, but rather they could be regarded as requiring selective alteration of pixels as needed.
International Patent Application No. WO 92/04710 disclosed a scheme in which any liquid crystal element is only driven on or off when a change of state therein is required, otherwise it remains unaddressed. Each pixel can therefore be subjected only to alternate turn-on and turn-off pixel pulses of well-defined and equal lengths, thus automatically affording dc balance in the long term.
The use of intervening uniformly blank images in the manner required by the present invention is not disclosed in this prior art.